The present invention relates to the field of semiconductor memories, and, more particularly to non-volatile memories the content of which is electrically alterable (programmable or programmable and erasable), such as EPROMs, EEPROMs and Flash EEPROMs.
A normal read operation (hereinafter, standard read) in a memory provides for supplying to the memory an address which identifies a corresponding location of the memory. After a specific time interval has elapsed, termed access time, the data stored in the location is available at the output of the memory.
Memories are known in which, besides the standard read operation, it is possible to carry out a page mode read operation which based upon only the less significant bits of the address being supplied at the input of the memory vary to obtain valid data at the output of the memory in a shorter time than the standard access time. Other known memories, however, in addition to the possibility of carrying out a standard read, have the possibility of carrying out a so-called burst mode read. By supplying to the memory an external clock signal and an address corresponding to an initial memory location, the memory internally increments the address automatically and delivers at the output new data corresponding to the successive memory addresses at each cycle of the clock signal. This read mode makes it possible to reduce significantly the access time in all those cases where, instead of accessing locations distributed randomly in the memory space, it is necessary to access a certain number of contiguous locations.
Also known are electrically programmable and erasable non-volatile memories organized in sectors, or portions of memory which can be erased and programmed independently of one another. Memories of this type may in addition have a functional capability termed temporary suspension of erasure (xe2x80x9cerase suspendxe2x80x9d) or of programming (xe2x80x9cprogram suspendxe2x80x9d), which makes it possible to suspend temporarily the operation of erasure or programming of a sector to carry out a standard read access to one of the other memory sectors. Since the read is however a standard type read, the possibilities of a reduction in the access time offered by the two read modes described previously are not utilized. Rapid access to the memory with a burst read or page read mode is only permitted on completion of the programming or erasure.
In view of the state of the art described, it is an object of the present invention to provide a memory having the functional capability of burst mode read and/or page mode read also while the erasure or programming of a sector is taking place.
According to the present invention, this object is achieved by provision of an electrically alterable semiconductor memory comprising a plurality of memory sectors, each having a content being individually electrically alterable; and a control circuit for controlling operation of electrical alteration of the content of the memory sectors, for permitting selective execution of an operation of electrical alteration of the content of one of the memory sectors with a possibility of suspending execution to permit read access to at least one other of the memory sectors, and for permitting during suspension a burst mode read operation of the at least one other memory sector. The control circuit may include a circuit for controlling the electrical alteration operations, a scanning circuit for scanning memory locations of the memory sectors, and a circuit for controlling the burst mode read operations. The memory according to the invention has the advantage of permitting, during the execution of an operation of erasure or programming of a memory sector, rapid access in burst mode or page mode to another memory sector.